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74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Rev. 03 -- 20 April 2005 Product data sheet
1. General description
The 74ABT544 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB and LEBA) and output enable (OEAB and OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64 mA. The 74ABT544 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B enable (EAB) input and the A-to-B latch enable (LEAB) input are LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-state B output buffers are active and invert the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA and OEBA inputs.
2. Features
s s s s s s s s s Combines 74ABT640 and 74ABT373 type functions in one device 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Output capability: +64 mA and -32 mA Live insertion and extraction permitted Power-up 3-state Power-up reset Latch-up protection: x JESD78: exceeds 500 mA s ESD protection: x MIL STD 883 method 3015: exceeds 2000 V x Machine model: exceeds 200 V
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
3. Quick reference data
Table 1: Quick reference data Tamb = 25 C; GND = 0 V. Symbol Parameter tPLH tPHL CI CI/O ICC propagation delay An to Bn or Bn to An propagation delay An to Bn or Bn to An input capacitance I/O capacitance quiescent supply current Conditions CL = 50 pF; VCC = 5 V CL = 50 pF; VCC = 5 V VI = 0 V or VCC outputs disabled; VO = 0 V or VCC outputs 3-state; VCC = 5.5 V Min Typ 3.0 3.6 4 7 110 Max Unit ns ns pF pF A
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74ABT544D 74ABT544N 74ABT544DB -40 C to +85 C -40 C to +85 C -40 C to +85 C SO24 DIP24 SSOP24 TSSOP24 Description plastic dual in-line package; 24 leads (300 mil) plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT222-1 SOT340-1 SOT355-1 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 Type number
74ABT544PW -40 C to +85 C
5. Functional diagram
2 23 1 13 11 14 3 13 2 4 5 6 7 22 21 20 19 18 17 16 15
001aac756
3
4
5
6
7
8
9
10
1EN3 (AB) G1 1C5 2EN4 (BA) G2 2C6 3 5D 5D 4 21 20 19 18 17 16 15
001aac757
11 23 14 1
A0 A1 A2 A3 A4 A5 A6 A7 EAB EBA LEAB LEBA B0 B1 B2 B3 B4 B5 B6 B7 OEAB OEBA
22
8 9 10
Fig 1. Logic symbol
Fig 2. IEC logic symbol
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Product data sheet
Rev. 03 -- 20 April 2005
2 of 19
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
OEBA
2 13 OEAB
EBA LEBA
23 1 11 14
EAB LEAB
DETAIL A D LE A0 3 Q D LE Q
22
B0
4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7
DETAIL A x 7
21 20 19 18 17 16 15
001aac758
B1 B2 B3 B4 B5 B6 B7
Fig 3. Logic diagram
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Product data sheet
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
6. Pinning information
6.1 Pinning
LEBA OEBA A0 A1 A2 A3 A4 A5 A6
1 2 3 4 5 6
24 VCC 23 EBA 22 B0 21 B1 20 B2 19 B3
544
7 8 9 18 B4 17 B5 16 B6 15 B7 14 LEAB 13 OEAB
001aac755
A7 10 EAB 11 GND 12
Fig 4. Pin configuration
6.2 Pin description
Table 3: Symbol LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 EAB GND OEAB LEAB B7 B6 B5 B4
9397 750 14756
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description B-to-A latch enable input (active LOW) B-to-A output enable input (active LOW) port A, 3-state output 0 port A, 3-state output 1 port A, 3-state output 2 port A, 3-state output 3 port A, 3-state output 4 port A, 3-state output 5 port A, 3-state output 6 port A, 3-state output 7 A-to-B enable input (active LOW) ground (0 V) A-to-B output enable input (active LOW) A-to-B latch enable input (active LOW) port B, 3-state output 7 port B, 3-state output 6 port B, 3-state output 5 port B, 3-state output 4
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Pin description ...continued Pin 19 20 21 22 23 24 Description port B, 3-state output 3 port B, 3-state output 2 port B, 3-state output 1 port B, 3-state output 0 B-to-A enable input (active LOW) supply voltage
Table 3: Symbol B3 B2 B1 B0 EBA VCC
7. Functional description
7.1 Function table
Table 4: Status Disabled Disabled + latch Latch + display Transparent Hold
[1]
Function table [1] Control OExx H X L L L L Exx X H L L L LExx X X L L H Input An or Bn X X h l h l H L X Output An or Bn Z Z Z Z L H L H NC
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don't care; = LOW-to-HIGH clock transition; NC = no change; Z = high-impedance OFF-state.
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tj Tstg
[1] [2]
Parameter supply voltage input voltage output voltage input diode current output diode current output current junction temperature storage temperature
Conditions
[1]
Min -0.5 -1.2 -0.5 [2]
Max +7.0 +7.0 +5.5 -18 -50 128 150 +150
Unit V V V mA mA mA C C
output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state
[1]
-65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6: Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VIH VIL IOH IOL t/V Tamb supply voltage input voltage HIGH-level input voltage LOW-level Input voltage HIGH-level output current LOW-level output current input transition rise or fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 0 -40 Typ Max 5.5 VCC 0.8 -32 64 10 +85 Unit V V V V mA mA ns/V C
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Product data sheet
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
10. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C VIK VOH input diode voltage HIGH-level output voltage VCC = 4.5 V; IIK = -18 mA VCC = 4.5 V; VI = VIL or VIH IOH = -3 mA IOH = -32 mA VCC = 5.0 V; VI = VIL or VIH IOH = -3 mA VOL VRST ILI LOW-level output voltage input leakage current control pins data pins IOFF IPU, IPD IOZ power-down leakage current VCC = 0 V; VI or VO 4.5 V
[2]
Conditions
Min 2.5 2.0 3.0 [1]
Typ -0.9 3.2 2.3 3.7 0.42 0.13 0.01 5 5.0 5.0
Max -1.2 0.55 0.55 1.0 100 100 50
Unit V V V V V V A A A A
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; VI = GND or 5.5 V
restart LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
-
power-up or power-down 3-state VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; output current VOExx = don't care 3-state output current VCC = 5.5 V; VI = VIL or VIH output HIGH-state at VO = 2.7 V output LOW-state at VO = 0.5 V
[3]
5.0 -5.0 5.0 -65 110 20 110 0.3 4 7 -
50 -50 50 -180 250 30 250 1.5 -1.2 0.55 0.55
A A A mA A mA A mA pF pF V V V V V V
ICEX IO ICC
output HIGH-state leakage current output current quiescent supply current
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs 3-state
-50 -
ICC CI CI/O VIK VOH
additional supply current per input pin input capacitance I/O capacitance input diode voltage HIGH-level output voltage
VCC = 5.5 V; one input at 3.4 V and other inputs at VCC or GND; VCC = 5.5 V VI = 0 V or VCC outputs disabled; VO = 0 V or VCC VCC = 4.5 V; IIK = -18 mA VCC = 4.5 V; VI = VIL or VIH IOH = -3 mA IOH = -32 mA VCC = 5.0 V; VI = VIL or VIH IOH = -3 mA
[4]
2.5 2.0 3.0 -
Tamb = -40 C to +85 C
VOL VRST
LOW-level output voltage
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
[1]
restart LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
-
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Product data sheet
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ILI input leakage current control pins data pins IOFF IPU, IPD IOZ power-down leakage current VCC = 0 V; VI or VO 4.5 V
[2]
Conditions VCC = 5.5 V; VI = GND or 5.5 V
Min -
Typ -
Max 1.0 100 100 50
Unit A A A A
power-up or power-down 3-state VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; output current VOExx = don't care 3-state output current VCC = 5.5 V; VI = VIL or VIH output HIGH-state at VO = 2.7 V output LOW-state at VO = 0.5 V
[3]
-
50 -50 50 -180 250 30 250 1.5
A A A mA A mA A mA
ICEX IO ICC
output HIGH-state leakage current output current quiescent supply current
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs 3-state
-50 -
ICC
additional supply current per input pin
VCC = 5.5 V; one input at 3.4 V and other inputs at VCC or GND; VCC = 5.5 V
[4]
-
[1] [2] [3] [4]
For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 % a transition time of up to 100 s is permitted. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V.
11. Dynamic characteristics
Table 8: Dynamic characteristics GND = 0 V; for test circuit see Figure 10. Symbol tPLH Parameter propagation delay An to Bn, Bn to An LEBA to An, LEAB to Bn tPHL propagation delay An to Bn, Bn to An LEBA to An, LEAB to Bn tPZH output enable time to HIGH-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn tPZL output enable time to LOW-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn
9397 750 14756
Conditions
Min
Typ
Max
Unit
Tamb = 25 C; VCC = 5.0 V see Figure 5 see Figure 5 and 6 see Figure 5 see Figure 5 and 6 see Figure 7 see Figure 7 see Figure 8 see Figure 8
Rev. 03 -- 20 April 2005
1.7 2.1 2.4 3.0 1.8 1.9 2.9 3.1
3.0 3.5 3.6 4.4 3.0 3.4 4.2 4.6
3.8 4.2 4.5 5.3 3.9 4.1 5.2 5.5
ns ns ns ns ns ns ns ns
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Product data sheet
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Table 8: Dynamic characteristics ...continued GND = 0 V; for test circuit see Figure 10. Symbol tPHZ Parameter output disable time from HIGH-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn tPLZ output disable time from LOW-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn tsu(H) set-up time HIGH An to LEAB, Bn to LEBA An to EAB, Bn to EBA tsu(L) set-up time LOW An to LEAB, Bn to LEBA An to EAB, Bn to EBA th(H) hold time HIGH An to LEAB, Bn to LEBA An to EAB, Bn to EBA th(L) hold time LOW An to LEAB, Bn to LEBA An to EAB, Bn to EBA twL tPLH pulse width LOW LEAB and LEBA propagation delay An to Bn, Bn to An LEBA to An, LEAB to Bn tPHL propagation delay An to Bn, Bn to An LEBA to An, LEAB to Bn tPZH output enable time to HIGH-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn tPZL output enable time to LOW-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn tPHZ output disable time from HIGH-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn tPLZ output disable time from LOW-level OEBA to An, OEAB to Bn EBA to An, EAB to Bn see Figure 8 see Figure 8 2.0 2.0 6.3 6.7 ns ns see Figure 7 see Figure 7 2.0 2.1 4.9 5.2 ns ns see Figure 8 see Figure 8 2.9 3.1 6.1 6.5 ns ns see Figure 7 see Figure 7 1.8 1.9 4.7 5.0 ns ns see Figure 5 see Figure 5 and 6 2.4 3.0 5.2 6.2 ns ns see Figure 5 see Figure 5 and 6 1.7 2.1 4.7 5.2 ns ns Tamb = -40 C to +85 C; VCC = 5.0 V 0.5 V see Figure 9 see Figure 9 see Figure 9 0.5 0.5 3.5 -1.3 -1.3 1.8 ns ns ns see Figure 9 see Figure 9 0.5 0.5 -0.3 -0.2 ns ns see Figure 9 see Figure 9 3.0 3.0 0.6 0.6 ns ns see Figure 9 see Figure 9 3.0 3.0 1.5 1.5 ns ns see Figure 8 see Figure 8 2.0 2.0 2.8 3.0 5.8 6.2 ns ns see Figure 7 see Figure 7 2.0 2.1 3.3 3.4 4.3 4.5 ns ns Conditions Min Typ Max Unit
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Product data sheet
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Table 8: Dynamic characteristics ...continued GND = 0 V; for test circuit see Figure 10. Symbol tsu(H) Parameter set-up time HIGH An to LEAB, Bn to LEBA An to EAB, Bn to EBA tsu(L) set-up time LOW An to LEAB, Bn to LEBA An to EAB, Bn to EBA th(H) hold time HIGH An to LEAB, Bn to LEBA An to EAB, Bn to EBA th(L) hold time LOW An to LEAB, Bn to LEBA An to EAB, Bn to EBA twL pulse width LOW LEAB and LEBA see Figure 9 see Figure 9 see Figure 9 0.5 0.5 3.5 ns ns ns see Figure 9 see Figure 9 0.5 0.5 ns ns see Figure 9 see Figure 9 3.0 3.0 ns ns see Figure 9 see Figure 9 3.0 3.0 ns ns Conditions Min Typ Max Unit
12. Waveforms
VI An, Bn, LEBA, LEAB input GND
t PHL VOH t PLH VM VM
An, Bn output
VOL
VM
VM
001aac759
VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay for inverting output
VI
LEBA, LEAB input GND
VM
VM
t PLH VOH
t PHL
An, Bn output
VOL
VM
VM
001aac761
VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Propagation delay for non-inverting output
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Product data sheet
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
VI OEAB, OEBA, EAB, EBA input GND VM VM
t PZH VOH An, Bn output VOL VM
t PHZ VOH - 0.3 V
001aac760
VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. 3-state output enable time to HIGH-level and output disable time from HIGH-level
VI
OEAB, OEBA, EAB, EBA input GND VM VM
t PZL
t PLZ
VOH
An, Bn output VM VOL + 0.3 V
001aac762
VOL
VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level
VOH
LEAB, LEBA input VM VM
VOL
t wL
VI
An, Bn input VM VM VM VM
GND
t su(H) t h(H) t su(L) t h(L)
001aac763
VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times and latch enable pulse width
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
13. Test information
tW VI negative pulse 0V 90 % VM 10 % t THL (t f) t TLH (t r) VI positive pulse 0V 10 % tW 90 % VM 90 % VM 10 %
001aac765
90 % VM 10 % t TLH (t r) t THL (t f)
VM = 1.5 V.
a. Input pulse definition
VEXT VCC VI DUT
RT CL RL RL
PULSE GENERATOR
VO
001aac764
Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
b. Test circuit for 3-state outputs Fig 10. Load circuitry for switching times Table 9: Input VI 3.0 V fi 1 MHz tW 500 ns tr, tf 2.5 ns Test data Load CL 50 pF RL 500 VEXT tPHZ, tPZH open tPLZ, tPZL 7.0 V tPLH, tPHL open
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74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
14. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT137-1 (SO24)
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
D
ME
seating plane
A2
A
L
A1 c Z e b1 wM (e 1) MH 13
b 24
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) UNIT mm inches A max. 4.7 0.185 A1 min. 0.38 0.015 A2 max. 3.94 0.155 b 1.63 1.14 0.064 0.045 b1 0.56 0.43 0.022 0.017 c 0.36 0.25 0.014 0.010 D (1) 31.9 31.5 1.256 1.240 E (1) 6.73 6.25 0.265 0.246 e 2.54 0.1 e1 7.62 0.3 L 3.51 3.05 0.138 0.120 ME 8.13 7.62 0.32 0.30 MH 10.03 7.62 0.395 0.300 w 0.25 0.01 Z (1) max. 2.05 0.081
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT222-1 REFERENCES IEC JEDEC MS-001 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-03-12
Fig 12. Package outline SOT222-1 (DIP24)
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 13. Package outline SOT340-1 (SSOP24)
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT355-1 (TSSOP24)
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Product data sheet
Rev. 03 -- 20 April 2005
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Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
15. Revision history
Table 10: Revision history Release date 20050420 Data sheet status Product data sheet Change notice Doc. number 9397 750 14756 Supersedes 74ABT544_2 Document ID 74ABT544_3 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 2; changed latch-up protection to JESD78. Table 1; changed typical values for propagation delay. Table 8; changed values for propagation delay, output enable time and output disable time. Product specification Product specification 9397 750 10752 74ABT544 -
74ABT544_2 74ABT544
20021118 19930701
9397 750 14756
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 20 April 2005
17 of 19
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
16. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14756
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 20 April 2005
18 of 19
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
20. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 18
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 April 2005 Document number: 9397 750 14756
Published in The Netherlands

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